As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, memory cell designs having a footprint no larger than 2F2 are increasingly desired to provide high density. However, because of parasitic resistance in bit lines and word lines, increasingly large arrays result in non-negligible voltage drops across these bit lines and word lines. To deal with this parasitic resistance problem, memory arrays are broken down into multiple tiles or sub-arrays such that the bit lines and word lines are shorter and, therefore, have lower voltage drops from end to end. However, each sub array or tile will always require some peripheral support circuitry and this extra peripheral support circuitry reduces in array efficiency. U.S. Pat. No. 7,376,008 by Shepard titled “SCR Matrix Storage Device” issued on May 20, 2008 (the '008 patent) describes a memory array constructed with Current Level Switching Devices (CLSD's) such as SCR's or four layer diodes. CLSD devices switch when a voltage level is exceeded and, as such, are to a certain extent analog devices as opposed to purely digital devices. Many memory design engineers are skilled in the digital logic design, but fewer engineers are trained in analog design.